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HFA1130
September 1998 File Number 3369.2
850MHz, Output Limiting, Low Distortion Current Feedback Operational Amplifier
The HFA1130 is a high speed wideband current feedback amplifier featuring programmable output limits. Built with Intersil's proprietary complementary bipolar UHF-1 process, it is the fastest monolithic amplifier available from any semiconductor manufacturer. This amplifier is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overdrive recovery times. The output limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation, following an overdrive condition. The HFA1130 offers significant performance improvements over the CLC500/501/502. A variety of packages and temperature grades are available. See the ordering information below for details. For /883 product refer to the HFA1130/883 datasheet.
Features
* User Programmable Output Voltage Limits * Low Distortion (30MHz, HD2). . . . . . . . . . . . . . . . . -56dBc * -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 850MHz * Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 2300V/s * Fast Settling Time (0.1%) . . . . . . . . . . . . . . . . . . . . . 11ns * Excellent Gain Flatness - (100MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.14dB - (50MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04dB - (30MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01dB * High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA * Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns
Applications
* Residue Amplifier * Video Switching and Routing * Pulse and Video Amplifiers * Wideband Amplifiers * RF/IF Signal Processing
Ordering Information
PART NUMBER (BRAND) HFA1130IP HFA1130IB (H1130I) HFA11XXEVAL TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld SOIC PKG. NO. E8.3 M8.15
* Flash A/D Driver * Medical Imaging Systems * Related Literature - AN9420, Current Feedback Theory - AN9202, HFA11XX Evaluation Fixture
DIP Evaluation Board for High-Speed Op Amps
The Op Amps With Fastest Edges
Pinout
HFA1130 (PDIP, SOIC) TOP VIEW
INPUT 220MHz SIGNAL
NC -IN +IN
1 2 3 4
8
VH V+ OUT VL
+
7 6 5
OUTPUT (AV = 2) HFA1130 OP AMP 0ns 25ns
V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HFA1130
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 130 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 170 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . -65oC to TA to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = 5V, AV = +1, RF = 510, RL = 100, Unless Otherwise Specified TEST CONDITIONS (NOTE 2) TEST LEVEL TEMP. (oC)
PARAMETER INPUT CHARACTERISTICS Input Offset Voltage (Note 3)
MIN
TYP
MAX
UNITS
A A
25 Full Full 25 Full 25 Full 25 Full Full 25 Full 25 Full Full 25 Full 25 Full 25 25 25 Full 25 25 25
40 38 45 42 25 2.5 -
2 10 46 50 25 40 20 12 40 1 6 50 20 2 3.0 4 18 21
6 10 40 65 40 50 50 60 7 10 15 27 30 -
mV mV V/oC dB dB dB dB A A nA/oC A/V A/V A A nA/oC A/V A/V A/V A/V k pF V nV/Hz pA/Hz pA/Hz
Input Offset Voltage Drift VIO CMRR VCM = 2V
C A A
VIO PSRR
VS = 1.25V
A A
Non-Inverting Input Bias Current (Note 3) +IBIAS Drift +IBIAS CMS
+IN = 0V
A A C
VCM = 2V
A A
Inverting Input Bias Current (Note 3)
-IN = 0V
A A
-IBIAS Drift -IBIAS CMS VCM = 2V
C A A
-IBIAS PSS
VS = 1.25V
A A
Non-Inverting Input Resistance Inverting Input Resistance Input Capacitance (Either Input) Input Common Mode Range Input Noise Voltage (Note 3) +Input Noise Current (Note 3) -Input Noise Current (Note 3) TRANSFER CHARACTERISTICS 100kHz 100kHz 100kHz
A C B C B B B
AV = +2, Unless Otherwise Specified B 25 300 k
Open Loop Transimpedance (Note 3)
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HFA1130
Electrical Specifications
VSUPPLY = 5V, AV = +1, RF = 510, RL = 100, Unless Otherwise Specified (Continued) TEST CONDITIONS VOUT = 0.2VP-P, AV = +1 VOUT = 0.2VP-P, AV = +2, RF = 360 4VP-P, AV = -1 To 100MHz To 50MHz To 30MHz DC to 100MHz NTSC, RL = 75 NTSC, RL = 75 (NOTE 2) TEST LEVEL B B B B B B B B B A TEMP. (oC) 25 25 Full 25 25 25 25 25 25 Full
PARAMETER -3dB Bandwidth (Note 3) -3dB Bandwidth Full Power Bandwidth Gain Flatness (Note 3) Gain Flatness Gain Flatness Linear Phase Deviation (Note 3) Differential Gain Differential Phase Minimum Stable Gain
MIN 530 1
TYP 850 670 300 0.14 0.04 0.01 0.6 0.03 0.05 -
MAX -
UNITS MHz MHz MHz dB dB dB Degrees % Degrees V/V
OUTPUT CHARACTERISTICS AV = +2, Unless Otherwise Specified Output Voltage (Note 3) AV = -1 A A Output Current RL = 50, AV = -1 A A DC Closed Loop Output Impedance (Note 3) 2nd Harmonic Distortion (Note 3) 3rd Harmonic Distortion (Note 3) 3rd Order Intercept (Note 3) 1dB Compression TRANSIENT RESPONSE Rise Time Overshoot (Note 3) Slew Rate 30MHz, VOUT = 2VP-P 30MHz, VOUT = 2VP-P 100MHz 100MHz AV = +2, Unless Otherwise Specified VOUT = 2.0V Step VOUT = 2.0V Step AV = +1, VOUT = 5VP-P AV = +2, VOUT = 5VP-P 0.1% Settling Time (Note 3) 0.2% Settling Time (Note 3) POWER SUPPLY CHARACTERISTICS Supply Voltage Range Supply Current (Note 3) B A A LIMITING CHARACTERISTICS Clamp Accuracy Clamped Overshoot Overdrive Recovery Time Full 25 Full 4.5 21 5.5 26 33 V mA mA VOUT = 2V to 0V VOUT = 2V to 0V B B B B B B 25 25 25 25 25 25 1850 900 10 1400 2300 11 7 ps % V/s V/s ns ns B B B B B 25 Full 25, 85 -40 25 25 25 25 25 3.0 2.5 50 35 20 15 3.3 3.0 60 50 0.07 -56 -80 30 20 V V mA mA dBc dBc dBm dBm
AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified VIN = 2V, AV = -1 VIN = 1V, Input tR/tF = 2ns VIN = 1V A B B 25 25 25 60 4 0.75 125 1.5 mV % ns
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HFA1130
Electrical Specifications
VSUPPLY = 5V, AV = +1, RF = 510, RL = 100, Unless Otherwise Specified (Continued) TEST CONDITIONS (NOTE 2) TEST LEVEL B B A VH or VL = 100mVP-P B TEMP. (oC) 25 25 25 25
PARAMETER Negative Clamp Range Positive Clamp Range Clamp Input Bias Current Clamp Input Bandwidth NOTES:
MIN -
TYP -5.0 to +2.0 -2.0 to +5.0 50 500
MAX 200 -
UNITS V V A MHz
2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 3. See Typical Performance Curves for more information.
Application Information
Optimum Feedback Resistor (RF)
The enclosed plots of inverting and non-inverting frequency response detail the performance of the HFA1100/1120 in various gains. Although the bandwidth dependency on ACL isn't as severe as that of a voltage feedback amplifier, there is an appreciable decrease in bandwidth at higher gains. This decrease can be minimized by taking advantage of the current feedback amplifier's unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and the RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier's bandwidth is inversely proportional to RF. The HFA1100, 1120 designs are optimized for a 510 RF, at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback causes the same problems due to the feedback impedance decrease at higher frequencies). At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth.
ACL +1 -1 +2 +5 +10 +19 RF () 510 430 360 150 180 270 BW (MHz) 850 580 670 520 240 125
output voltage at VH or VL ( the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 1 shows a simplified schematic of the HFA1130 input stage, and the high clamp (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of (V-IN - VOUT)/RF. This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches it's quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage.
V+ QP3 QP4 50K (30K FOR VL ) Z +1 VH QN5 QP2 QP5 QN6 QP6 QN4 200
QN2 QP1 +IN VV+ QN1 ICLAMP
R1
QN3
Clamp Operation
General
The HFA1130 features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5) of the amplifier. VH sets the upper output limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the
V-IN RF (EXTERNAL) VOUT
FIGURE 1. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
Tracing the path from VH to Z illustrates the effect of the clamp voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5. QP5 begins to conduct whenever the high impedance node
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HFA1130
reaches a voltage equal to QP5's base + 2VBE (QP5 and QN5). Thus, QP5 clamps node Z whenever Z reaches VH. R1 provides a pull-up network to ensure functionality with the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by VL. When the output is clamped, the negative input continues to source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as (V-IN - VOUT)/RF. As an example, a unity gain circuit with VIN = 2V, VH = 1V, and RF = 510 would have ICLAMP = (2-1)/510 = 1.96mA. Note that ICC will increase by ICLAMP when the output is clamp limited. return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of "Unclamped Performance" and "Clamped Performance" highlight the HFA1130's subnanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 4.0ns for the unclamped pulse, and 4.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1130 propagation delay is 500ps.
Use of Die in Hybrid Applications
This amplifier is designed with compensation to negate the package parasitics that typically lead to instabilities. As a result, the use of die in hybrid applications results in overcompensated performance due to lower parasitic capacitances. Reducing RF below the recommended values for packaged units will solve the problem. For AV = +2 the recommended starting point is 300, while unity gain applications should try 400.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 1, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP. VBE increases as ICLAMP increases, causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (V-IN -VOUTCLAMPED) and RF,so clamp accuracy degrades as the overdrive increases, or as RF decreases. As an example, the specified accuracy of 60mV for a 2X overdrive with RF = 510 degrades to 220mV for RF = 240 at the same overdrive, or to 250mV for a 3X overdrive with RF = 510. Consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity. The "Nonlinearity Near Clamp Voltage" curve in the data sheet illustrates the impact of several clamp levels on linearity.
PC Board Layout
The frequency performance of this amplifier depends a great deal on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value chip (0.1F) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and may cause oscillations. In most cases, the oscillation can be avoided by placing a resistor in series with the output. Care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown below.
Clamp Range
Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HFA1130 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won't be in a DC output voltage from an AC input signal. A 150 - 200mV AC signal will still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP /AVCL) the amplifier will
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HFA1130 Evaluation Board
An evaluation board is available for the HFA1130, (Part Number HFA11XXEVAL). Please contact your local sales office for information. The layout and schematic of the board are shown here:
+IN 500 500 VH 1 50 IN 2 3 4 10F 0.1F -5V GND 8 7 50 6 5 GND OUT VL 0.1F 10F +5V OUT V+ VL VGND 1
TOP LAYOUT
VH
BOTTOM LAYOUT
FIGURE 2. BOARD SCHEMATIC
Typical Performance Curves
AV = +2 120 90 OUTPUT VOLTAGE (mV)
VSUPPLY = 5V, RF = 510, TA = 25oC, RL = 100, Unless Otherwise Specified
AV = +2 1.2 0.9 OUTPUT VOLTAGE (V) TIME (5ns/DIV.) 0.6 0.3 0 -0.3 -0.6 -0.9 -1.2 TIME (5ns/DIV.)
60 30 0 -30 -60 -90 -120
FIGURE 3. SMALL SIGNAL PULSE RESPONSE
FIGURE 4. LARGE SIGNAL PULSE RESPONSE
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HFA1130 Typical Performance Curves
VSUPPLY = 5V, RF = 510, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
IN 0V TO 0.5V
IN 0V TO 1V
OUT 0V TO 1V
OUT 0V TO 1V
AV = +2, VH = 2V, VL = -2V TIME (10ns/DIV.)
AV = +2, VH = 1V, VL = -1V, 2X OVERDRIVE TIME (10ns/DIV.)
FIGURE 5. UNCLAMPED PERFORMANCE
FIGURE 6. CLAMPED PERFORMANCE
NORMALIZED GAIN (dB)
0 -3 -6 -9 -12
VOUT = 200mVP-P GAIN AV = +1 AV = +2 AV = +6 AV = +11 0 AV = +1 AV = +2 AV = +6 AV = +11 0.3 1 10 100 FREQUENCY (MHz) -90 -180 -270 -360 1K PHASE (DEGREES) PHASE
NORMALIZED GAIN (dB)
VOUT = 200mVP-P 0 -3 -6 -9 -12 180 AV = -1 AV = -5 AV = -10 AV = -20 0.3 1 10 100 FREQUENCY (MHz) 90 0 -90 -180 1K PHASE (DEGREES) PHASE (DEGREES) PHASE GAIN AV = -1 AV = -5 AV = -10 AV = -20
FIGURE 7. NON-INVERTING FREQUENCY RESPONSE
FIGURE 8. INVERTING FREQUENCY RESPONSE
6 GAIN (dB) 3 0 -3 -6
NORMALIZED GAIN (dB)
AV = +1, VOUT = 200mVP-P RL = 1k GAIN RL = 100 RL = 50 PHASE (DEGREES) PHASE RL = 50 RL = 100 RL = 1k RL = 100 RL = 1k
AV = +2, VOUT = 200mVP-P 3 0 -3 -6 PHASE RL = 50 RL = 100 GAIN RL = 100 RL = 50 0 -90 RL = 1k RL = 100 RL = 1k 0.3 1 10 FREQUENCY (MHz) 100 -180 -270 -360 1K RL = 1k
0 -90 -180 -270 -360 1K
0.3
1
10 100 FREQUENCY (MHz)
FIGURE 9. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
FIGURE 10. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
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HFA1130 Typical Performance Curves
AV = +1
VSUPPLY = 5V, RF = 510, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB)
20 10 GAIN (dB) 0 -10 -20 -30
0.160VP-P
20 10 0 -10 -20 -30
AV = +2 0.32VP-P
0.500VP-P 0.920VP-P 1.63VP-P
1.00VP-P 1.84VP-P 3.26VP-P
0.3
1
10 FREQUENCY (MHz)
100
1K
0.3
1
10 FREQUENCY (MHz)
100
1K
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
NORMALIZED GAIN (dB)
20 10 0 -10 -20 -30
AV = +6
AV = +1 950 BANDWIDTH (MHz) 900 850 800 750 700
0.96VP-P TO 3.89VP-P
0.3
1
10 FREQUENCY (MHz)
100
1K
-50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
FIGURE 14. -3dB BANDWIDTH vs TEMPERATURE
AV = +2
+2.0 +1.5 DEVIATION (DEGREES)
AV = +2
0 GAIN (dB) -0.05 -0.10 -0.15 -0.20
+1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0
1
10 FREQUENCY (MHz)
100
0
15
30
45
60
75
90
105
120
135
150
FREQUENCY (MHz)
FIGURE 15. GAIN FLATNESS
FIGURE 16. DEVIATION FROM LINEAR PHASE
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HFA1130 Typical Performance Curves
250
VSUPPLY = 5V, RF = 510, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
AV = -1 0.6
AV = +2, VOUT = 2V
GAIN (k)
25
SETTLING ERROR (%)
GAIN
0.4 0.2 0 -0.2 -0.4 -0.6
2.5 PHASE
180 135 90 45 0
0.25
0.01
0.1
1 10 FREQUENCY (MHz)
100
500
PHASE (DEGREES)
-4
1
6
11
16
21 26 TIME (ns)
31
36
41
46
FIGURE 17. OPEN LOOP TRANSIMPEDANCE
FIGURE 18. SETTLING RESPONSE
40 1000 OUTPUT RESISTANCE () INTERCEPT POINT (dBm) 2-TONE 35 30 25 20 15 10 5 0 0.3 1 10 100 FREQUENCY (MHz) 1000 0 100 200 300 FREQUENCY (MHz) 400
100
10
1
0.1
FIGURE 19. CLOSED LOOP OUTPUT RESISTANCE
-30 -35 -40 DISTORTION (dBc) DISTORTION (dBc) 100MHz -45 -50 -55 -60 -65 -70 -5 -3 -1 1 3 5 7 9 11 13 15 30MHz 50MHz
FIGURE 20. 3rd ORDER INTERMODULATION INTERCEPT
-30 -40 -50 100MHz -60 -70 -80 -90 -100 -110 -5 -3 -1 1 3 5 7 9 11 13 15 30MHz 50MHz
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 21. 2nd HARMONIC DISTORTION vs POUT
FIGURE 22. 3rd HARMONIC DISTORTION vs POUT
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HFA1130 Typical Performance Curves
38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6
VSUPPLY = 5V, RF = 510, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
AV = +1 35 30 25 20 15 10 5 0 RF = 510 VOUT = 2VP-P RF = 510 VOUT = 0.5VP-P 300 400 500 600 700 INPUT RISE TIME (ps) 800 900 1000 RF = 360 VOUT = 0.5VP-P RF = 360 VOUT = 1VP-P RF = 360 VOUT = 2VP-P AV = +2
VOUT = 1VP-P OVERSHOOT (%)
OVERSHOOT (%)
VOUT = 0.5VP-P
VOUT = 2VP-P
RF = 510 VOUT = 1VP-P
100
200
300
400 500 600 700 INPUT RISE TIME (ps)
800
900
1000
100
200
FIGURE 23. OVERSHOOT vs INPUT RISE TIME
FIGURE 24. OVERSHOOT vs INPUT RISE TIME
36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 360 400
25 AV = +2, tR = 200ps, VOUT = 2VP-P 24 SUPPLY CURRENT (mA) 440 480 520 560 600 FEEDBACK RESISTOR () 640 680 23 22 21 20 19 18 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 120
OVERSHOOT (%)
FIGURE 25. OVERSHOOT vs FEEDBACK RESISTOR
FIGURE 26. SUPPLY CURRENT vs TEMPERATURE
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 6 7 8 9 TOTAL SUPPLY VOLTAGE (V+ - V-, V) 10
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 -60 -40 -20
+IBIAS VIO
-IBIAS
45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
INPUT OFFSET VOLTAGE (mV)
SUPPLY CURRENT (mA)
0 20 40 60 80 TEMPERATURE (oC)
100 120
FIGURE 27. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 28. VIO AND BIAS CURRENTS vs TEMPERATURE
10
BIAS CURRENTS (A)
HFA1130 Typical Performance Curves
VSUPPLY = 5V, RF = 510, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
3.7 3.6 3.5 OUTPUT VOLTAGE (V) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) 0 100 1K 10K FREQUENCY (Hz) (AV = -1, RL = 50) | - VOUT | +VOUT NOISE VOLTAGE (nV/Hz) 30 25 20 15 10 5 300 275 225 200 175 150 125 100 75 ENI INIINI+ 100K 50 25 0 NOISE CURRENT (pA/Hz) 250
FIGURE 29. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 30. INPUT NOISE vs FREQUENCY
20 15 VL = -3V VOUT - (AV VIN) (mV) 10 5 0 -5 -10 -15 AV = -1, RL = 100 -20 -3 -2 -1 0 AV VIN (V) 1 2 3 VH = 1V VH = 2V VH = 3V VL = -2V VL = -1V
FIGURE 31. NON-LINEARITY NEAR CLAMP VOLTAGE
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HFA1130 Die Characteristics
DIE DIMENSIONS: 63 mils x 44 mils x 19 mils 1600m x 1130m METALLIZATION: Type: Metal 1: AlCu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: ALCu(2%) Thickness: Metal 2: 16kA 0.8kA PASSIVATION: Type: Nitride Thickness: 4kA 0.5kA TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1130
+IN
-IN
V-
BAL VL
BAL
VH
V+
OUT
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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